AMD, ARM, Intel, Qualcomm, Samsung, TSMC and other ten giants are together! Create chiplet interoperability specifications - Your-Tech

AMD, ARM, Intel, Qualcomm, Samsung, TSMC and other ten giants are together! Create chiplet interoperability specifications

On March 2, ASE, AMD, ARM, Google Cloud, Intel, Meta (Facebook), Microsoft, Qualcomm, Samsung, and TSMC jointly announced the establishment of an industry alliance to jointly create chiplet interconnect standards and promote an open ecosystem. , and developed the standard specification “UCIe”.

The full name of the UCIe standard is “Universal Chiplet Interconnect Express” (Universal Chiplet Interconnect Channel ), which establishes a unified standard for interconnection at the chip packaging level.

The UCIe 1.0 standard defines the inter-chip I/O physical layer, inter-chip protocol, software stack, etc., and utilizes two mature high-speed interconnect standards, PCIe and CXL.

The standard was originally proposed and formulated by Intel, and was later opened to the industry for joint development.

The UCIe standard is open to the whole industry. The relevant white papers are available for download , and the specification can also be obtained by contacting the UCIe Alliance.

With the changes in industries and technologies, the difficulty and cost of traditional single-process and single-chip practices are getting higher and higher, and changes are urgently needed.

Data shows that the design cost of a 10nm chip is $174.4 million, a 7nm chip has soared to $297.8 million, and a 5nm chip is as high as $542.2 million. Even industry giants are struggling.

To this end, while promoting advanced technology, chip giants are also making every effort to develop new packaging technology, integrating multiple small chips with different processes and different functions through 2D, 2.5D, 3D and other methods. More flexibility to manufacture large chips.

AMD’s current Ryzen and Xiaolong processors, and Intel’s future Core and Xeon processors are all typical small chips.

The Intel Ponte Vecchio computing accelerator card is a master piece. Up to 63 Tile small chip units are packaged in a space of 4844 square millimeters, using five different manufacturing processes, and the total number of transistors exceeds 1000.

Of course, in the past, small chip packaging was done by each manufacturer on its own, and the new UCIe standard specification makes it possible for small chips from different manufacturers to communicate with each other , allowing chips from different manufacturers, different processes, different architectures, and different functions to mix and match, x86, It is not impossible to integrate ARM and RISC-V together.

In fact, just a few days ago, Intel clearly proposed to promote an open chiplet platform and create modular products across diverse instruction sets including but not limited to x86, ARM, and RISC-V.

Obviously, Intel was talking about this UCIe alliance at the time.